NPTEL Advanced Computer Architecture Week 10 Assignment Answers 2025

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NPTEL Advanced Computer Architecture Week 10 Assignment Answers 2025

1. Consider the following statements and select the most appropriate option.

S1: PLSC (Per Location Sequential Consistency) is needed to provide the illusion of a single memory location, even if we have a distributed cache.
S2: To achieve high performance in multi-core systems, we need to sacrifice PLSC (Per Location Sequential Consistency).

  • Only S1 is true
  • Only S2 is true
  • Both S1 and S2 are true
  • Both S1 and S2 are false
Answer :- For Answers Click Here

2. When a write operation is observed by all threads, it is referred to as _____________.

  • Write serialization
  • Write validation
  • Write propagation
  • Write localization
Answer :-

3. Consider the following statements and select the most appropriate option.

S1: If an execution is in PLSC, it will also be in SC.
S2: Ensuring SC in multithreaded execution will prohibit many performance enhancing optimizations in out-of-order machines.

  • Only S1 is true
  • Only S2 is true
  • Both S1 and S2 are true
  • Both S1 and S2 are false
Answer :-

4. An execution containing non-atomic writes ____________ comply with PLSC. Allowing processors or cache controllers to reorder accesses to the same address will ____________ the program order.

  • can, affect
  • can, not affect
  • cannot, affect
  • cannot, not affect
Answer :-

5. Which of the following statements is NOT correct?

  • The fence instruction is an example of a memory barrier.
  • The release instruction can only complete if all the instructions before it have been fully completed.
  • No instruction after the acquire instruction in program order can execute before it has completed.
  • The release instruction does not allow instructions after it to execute before it has completed.
Answer :-

6. Consider the following statements and select the most appropriate option.

S1: The valid outcomes for a given piece of parallel code are dependent on the memory model of the machine.
S2: We can create an execution witness for both a valid and an invalid execution of a parallel code.

  • Only S1 is true
  • Only S2 is true
  • Both S1 and S2 are true
  • Both S1 and S2 are false
Answer :- For Answers Click Here

7. Which among the following edges are not always global in memory models other than SC?

E1: PORW
E2: PORR
E3: POWW
E4: POIS

  • E1 and E4
  • E1 and E3
  • E1, E3 and E4
  • E1, E2 and E3
Answer :-

8. The rfe edge is ____________if writes are atomic. The rfi edge is ___________when we have optimizations like load-store forwarding.

  • global, global
  • not global, global
  • global, not global
  • not global, not global
Answer :-

9. Consider the following statements and select the most appropriate option.

S1: The ws edge is a global edge as a consequence of PLSC.
S2: The fr edge is a global edge because of PLSC.

  • Only S1 is true
  • Only S2 is true
  • Both S1 and S2 are true
  • Both S1 and S2 are false
Answer :-

10. Consider the following statements and select the correct option.

S1: If every access graph is cyclic, then PLSC is upheld across all memory locations.
S2: An acyclic causal graph ensures the absence of ‘thin air reads’.

  • Only S1 is true
  • Only S2 is true
  • Both S1 and S2 are true
  • Both S1 and S2 are false
Answer :- For Answers Click Here

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