NPTEL Advanced Computer Architecture Week 11 Assignment Answers 2025
1. Cache coherence protocols that use buses are known as __________protocols. In____________ protocols all the messages are essentially broadcast messages.
- snoopy, snoopy
- snoopy, directory
- directory, directory
- directory, snoopy
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2. Consider the following statements and select the correct option.
S1: In snoopy coherence protocols, a shared state allows seamless evictions.
S2: If we need to write, the write is broadcasted first to the rest of the sister caches.
- Only S1 is true
- Only S2 is true
- Both S1 and S2 are true
- Both S1 and S2 are false
Answer :-
3. Consider the following statements and select the correct option.
S1: A single-writer multiple-reader model for each cache line ensures a global order of ‘writes’ to the same memory location.
S2: If any line is in the modified state and another cache requests the block for a read, no state transition is needed anywhere.
- Only S1 is true
- Only S2 is true
- Both S1 and S2 are true
- Both S1 and S2 are false
Answer :-
4. In the MOESI protocol, whenever another cache requests data that is in a/an ____________ state, the line moves to the O state. An eviction from the ________ state leaves us with the case where there is no owner.
- E, O
- S, S
- M, S
- S, O
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5. Consider the following statements and select the correct option.
S1: A distributed directory solves the issue of a single point of contention in the directory protocol.
S2: In uniprocessor systems, false sharing can cause inefficiency.
- Only S1 is true
- Only S2 is true
- Both S1 and S2 are true
- Both S1 and S2 are false
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6. Which among the following is not an atomic operation?
- Test and Set
- Compare and Set
- Fetch and Add
- Fetch and Decode
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7. A/an ______________ algorithm ensures no starvation.
- Altruistic
- Lock-free
- Test and set
- Compare and set
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8. If there are very aggressive optimizations in the processor architecture, the memory model has to be very _____________. PLSC requires the ______________ order to always be global.
- weak, rf
- weak, fr
- strong, rf
- strong, fr
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9. In which of the following memory models is the R→R ordering relaxed?
- SC
- TSO
- Processor Consistency
- Weak Ordering
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10. Two accesses are said to be concurrent when there is no path between them in the execution witness that contains a/an ___________ edge.
- so
- po
- ws
- rf
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