NPTEL Advanced Computer Architecture Week 3 Assignment Answers 2025

NPTEL Advanced Computer Architecture Week 3 Assignment Answers 2025

1. In the case of ____________instructions it is _____________to fetch multiple instructions at once since the boundaries between instructions are _______________.

  • CISC, easy, known
  • RISC, easy, not known
  • CISC, hard, not known
  • RISC, hard, known
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2. Select the most appropriate option. Answer in the context of load instructions that use the stack pointer as the argument.

S1: We cannot compute the address of the load instruction at decode time.
S2: We cannot issue a load to the memory system based on the stack pointer’s value early.

  • S1 is true, S2 is false
  • S1 is false, S2 is true
  • Both S1 and S2 are true
  • Both S1 and S2 are false
Answer :- 

3. In an out-of-order processor, we “appear to” update the architectural registers in program order to _______________.

  • provide a speedup.
  • ensure precise exceptions.
  • handle WAR and WAW dependencies.
  • All the options.
Answer :- 

4. Consider a system with 16 architectural registers and 128 physical registers. At any point of time, there will at least be _____________ physical registers that are unmapped.

  • 16
  • 128
  • 112
  • 144
Answer :- 

5. Select the most appropriate option for the rename stage of an out-of-order processor.

S1: The dependency check logic translates an architectural register ID to a physical register ID to remove WAR and WAW dependencies.
S2: The register alias table keeps track of the available and free physical register IDs.

  • S1 is true, S2 is false
  • S1 is false, S2 is true
  • Both S1 and S2 are true
  • Both S1 and S2 are false
Answer :- 

6. What does the ready bit of an entry in the instruction window signify?

  • The corresponding value is present in the physical register file.
  • The corresponding value is present in the architectural register file.
  • The corresponding value can be stored in the physical register file.
  • The corresponding value can be stored in the architectural register file.
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7. The process of sending instructions from the instruction window to the execution units is called

  • Instruction dispatch
  • Instruction execution
  • Instruction scheduling
  • Instruction issue
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8. A producer instruction broadcasts its value after it

  • executes
  • gets selected
  • writes back
  • is dispatched
Answer :- 

9. Why do we prefer a large number of physical registers?

S1: To increase Instruction Level Parallelism (ILP)
S2: To have a large number of instructions in flight

  • Only S1
  • Only S2
  • Both S1 and S2
  • Neither S1 nor S2
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10. In general, which of the following select policies is the most performance-efficient?

  • Load instructions have higher priority than stores.
  • Store instructions have higher priority than loads.
  • Load and store instructions have the same priority.
  • The priority of load and store instructions depends on the nature of an application.
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