NPTEL Advanced Computer Architecture Week 4 Assignment Answers 2025
1. In an out-of-order pipeline, stores have to be sent to the memory system in ________ order.
- program
- out-of-order
- data dependence
- Depends on the processor
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2. In a load-store queue, under which conditions do we access the d-cache while processing a load?
C1: We encounter a store to the same address while searching all the stores before it.
C2: We encounter a store with an unresolved address while searching all the stores before it.
- Only C1
- Only C2
- Both C1 and C2
- Neither S1 nor S2
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3. When we encounter a store in a load-store queue, we search all the ______________ it.
- stores after it
- loads and stores after it
- stores before it
- loads and stores before it
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4. After _____________ an instruction, we add it to the reorder buffer.
- decoding
- selecting
- executing
- fetching
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5. When the instruction that has had an exception becomes the earliest entry, we remove all the entries from the ____________.
- Instruction window
- Load store queue
- Reorder buffer
- All the options
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6. Select the most appropriate option for a content addressable memory.
S1: We address each element by its content.
S2: It is slower than a structure that is addressed by an index.
- S1 is true, S2 is false
- S1 is false, S2 is true
- Both S1 and S2 are true
- Both S1 and S2 are false
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7. When a load instruction is predicted to be colliding, it has to wait in the load store queue till all the preceding stores are __________. The performance of the load-store dependence predictor can be improved by storing the ___________information between the colliding load and store.
- committed, history
- committed, distance
- resolved, history
- resolved, distance
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8. In the case of memory dependencies, the load->store dependence is like a __________ dependence and the store-> load dependence is like a ____________ dependence
- WAR (Write after Read), RAW (Read after Write)
- RAW (Read after Write), WAW (Write after Write)
- RAW (Read after Write), WAR (Write after Read)
- WAW (Write after Write), RAW (Read after Write)
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9. Which of the following statements are correct regarding the retirement register file?
- It maintains the state of all architectural registers at commit time.
- Each entry of the reorder buffer is augmented with the value of the destination register.
- It writes the value of the destination register at commit time.
- All the options
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10. A/An____________ based RAT (register alias table) is much slower than a/an___________ based RAT of equivalent size. Additionally, a/an___________ based RAT consumes more power.
- SRAM, CAM, CAM
- CAM, SRAM, CAM
- CAM, SRAM, SRAM
- SRAM, CAM, SRAM
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