NPTEL Advanced Computer Architecture Week 6 Assignment Answers 2025
1. Which of the following statements are correct regarding EPIC and VLIW processors.
S1: VLIW processors can be called an advanced avatar of EPIC processors.
S2: In VLIW processors, instructions are bundled into very long words.
- S1 is true, S2 is false
- S1 is false, S2 is true
- Both S1 and S2 are true
- Both S1 and S2 are false
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2. Which among the following is not a type of branch predictor in Intel Itanium processors?
- Compiler directed
- PAp Predictor
- Multi-way branches
- Loop-fusion predictor
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3. Which of the following are not present in Intel Itanium processors?
- Instruction Window
- Wakeup
- Select Unit
- All the options
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4. In Itanium processors, each bundle annotates its resource requirements, which is essential to avoid_________________.
- Starvation
- Data hazards
- Control hazards
- Structural hazards
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5. In PLAs (Programmable Logic Arrays), the _____________plane computes the minterms. Different Boolean functions can be implemented in the _____________plane.
- AND, AND
- OR, OR
- OR, AND
- AND, OR
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6. Which of the following is correct regarding raster graphics?
- In raster graphics, we store an image as a matrix of pixels.
- For stretching and transforming an image, raster graphics is better than vector graphics.
- Generally, we do not prefer raster graphics when we work with photographs.
- All the options.
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7. Which of the following is correct regarding shader programs?
- It is a custom language to work with objects, vertices, and pixels.
- It applies the following transformations to images: rotation, skewing, etc.
- It applies the following effects to images: textures, shading, and illumination.
- All the options.
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8. The correct ordering of the basic units of a graphics processing pipeline is:
- Vertex processor → Rasterizer → Pixel engine → Fragment processor
- Rasterizer → Vertex processor → Pixel engine → Fragment processor
- Vertex processor → Rasterizer → Fragment processor → Pixel engine
- Vertex processor → Pixel engine → Fragment processor → Rasterizer
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9. Which of the following statements is incorrect regarding NVIDIA’s CUDA toolkit?
- The GPU component of a program is compiled into PTX.
- The dynamic PTX to SASS compilation takes place at compile time.
- The CUDA command nvcc compiles the GPU code and the CPU code.
- None of these.
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10. A barrier is a _____ within a thread block. Each thread block works ___________- the other thread blocks.
- synchronization point, independent of
- termination point, independent of
- synchronization point, in synchronization with
- termination point, in synchronization with
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