NPTEL Advanced Computer Architecture Week 9 Assignment Answers 2025
1. A basic block in a trace cache is a set of instructions with ____________point(s) of entry and_____________point(s) of exit.
- a single, a single
- a single, multiple
- multiple, single
- multiple, multiple
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2. The buffer locally constructs the trace segment in a trace cache. Trace segments are stored in consecutive ________________.
- Fill, cache banks
- Fill, sets
- Trace, cache banks
- Trace, sets
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3. Consider a case where i-cache misses have high repeatability and there is high correlation between consecutive misses (e.g., miss sequence A B … A B … A B … A B …). Which type of prefetcher leverages these types of patterns?
- Next line prefetcher
- Next block prefetcher
- Markov prefetcher
- Call graph prefetcher
Answer :-
4. The ____ predicts and prefetches at the granularity of functions. The _____ leverages the spacial locality property.
- Call graph prefetcher, next line prefetcher
- Markov prefetcher, next line prefetcher
- Call graph prefetcher, Markov prefetcher
- Next line prefetcher, call graph prefetcher
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5. Why do prefetchers operate on the miss sequence of a cache, and not on the access sequence?
- We only need to prefetch data/instructions for those block addresses that may record misses in the cache.
- The access sequence cannot be determined.
- We only need to prefetch data/instructions for those block addresses that may record hits in the cache.
- None of these.
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6. Consider the following statements and select the most appropriate option.
S1: Shared memory is easier to program than message passing.
S2: Shared memory is more scalable compared to message passing.
- Only S1 is true
- Only S2 is true
- Both S1 and S2 are true
- Both S1 and S2 are false
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7. Consider the following statements and select the most appropriate option.
S1: According to Ahmdal’s Law, the potential speedup is limited by the portion of the computation that cannot be parallelized.
S2: The Gustafson-Barsis’s law assumes that the parallel portion of the work scales with the number of processing units.
- Only S1 is true
- Only S2 is true
- Both S1 and S2 are true
- Both S1 and S2 are false
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8. Which category in the Flynn’s classification allows multiple processors to work independently on different tasks?
- SISD
- SIMD
- MISD
- MIMD
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9. Given a parallel program, the set of valid outcomes depends on the system on which the program is running. Which among the following specific aspects of the “system” determine the outcome?
1) The pipeline
2) Memory system
3) Network-on-chip (NoC)
4) Memory controller (for off-chip memory)
Options:
- 1 and 2
- 1, 2, and 3
- Only 2
- 1, 2, 3 and 4
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10. Consider the following statements and select the appropriate option.
S1: A multithreaded program always produces the same outcome irrespective of the relative order of scheduling of threads and the behavior of memory operations.
S2: Coherence is a subset of the overall memory model that specifies the behavior with respect to a single location
- Only S1 is true
- Only S2 is true
- Both S1 and S2 are true
- Both S1 and S2 are false
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