NPTEL Digital System Design Week 4 Assignment Answers 2025

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NPTEL Digital System Design Week 4 Assignment Answers 2025

1. How many functions of type f(x,y,z) = f(x’,y’,z’) can be formed from boolean functions with three variables x,y,z.

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2. A logic circuit is implemented by the boolean function f = x’y+xy’z’. It is found that the input combination x=y=1 can never occur. Taking this into account, a simplified expression for “f” is?

  • x+yz’
  • y+xz’
  • z+xy’
  • x+y’z
Answer :-

Linked Question 4-5: Consider the below-given K-map, and answer the following questions

4. Identify the number of prime implicants.

Answer :-

5. Identify the number of essential prime implicants.

Answer :-

Linked Question 6-7: Consider the below given K-map, and answer the following questions

6. Identify the number of prime implicants.

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7. Identify the number of essential prime implicants.

Answer :-

8. For the boolean function as F(A,B,C) = ∑(0,1,3,5) + d(2,4), draw the K-map and find the minimum boolean expression

  • F(A,B,C) = A’ + B’
  • F(A,B,C) = A’.B’
  • F(A,B,C) = (A.B)’
  • F(A,B,C) = (A+B)’
  • F(A,B,C) = A’.1 + B’.1
Answer :-

9. Simplify the boolean function F(W, X, Y, Z) = m(1,3,7,11,15) with don’t care conditions d(W,X,Y,Z) = m(0,2,5).

  • F = ((W+Z’).(Y’+Z’))’
  • F = W’Z + YZ’
  • F = WZ’ + YZ
  • F = (W’Z’)’.(YZ)
Answer :-

Linked Questions 10-11:

Consider the below truth table

10. For the given truth table, draw the Karnaugh Map (K-map) and obtain the minimized Boolean expression in Sum of Products (SOP) form. Then, determine the number of NAND gates required to implement the minimized Boolean expression using NAND gate realization. [You need to enter the total number of NAND gates required]

Answer :-

11. For the given truth table, draw the complemented Karnaugh Map (K-map) and obtain the minimized Boolean expression in the Product of sum form (POS) form. Then, determine the number of NOR gates required to implement the minimized Boolean expression using NOR gate realization. [You need to enter the total number of NOR gates required]

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12. Using K-Map, the following equation, D = AC + A’C + C’, simplifies to?

  • AC
  • A’C
  • C
  • 0
  • 1
  • C(A+A’)
  • C’
Answer :-

13. Karnaugh map is used to

  • minimise the number of flip-flops in a digital circuits
  • to design gates
  • to minimise the number of gates in only a digital circuit .
  • to minimise the number of gates and fan-in requirements of the gates in a digital circuit
Answer :-

14. In K-map simplification, a group of eight adjacent ones leads to a term with

  • one literal less than the total number of variables
  • two literals less than the total number of variables
  • three literals less than the total number of variables
  • four literals less than the total number of variables
Answer :-

15. How many 2-input NAND gates are required to implement F = ABC + AD + C’D’

Answers :-

16. In Verilog, when designing a multi-bit adder using assign statements, what would be the consequence of using a blocking assignment (=) in the combinational logic for the sum calculation?

  • The adder will exhibit correct parallelism, as blocking assignments immediately update values in the current time step.
  • The adder will work correctly, but with increased delay because values will be updated sequentially.
  • The adder will work correctly for all bit-widths but fail for high bit-widths due to simulation inaccuracies.
  • The adder will fail to propagate the correct sum value in simulation.
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