NPTEL Digital System Design Week 6 Assignment Answers 2025
1. A circuit is designed to add ten single-bit operands. Which of the following adder architectures would use the least number of gates?
- Ripple Carry Adder
- Carry Select Adder
- Carry Look-Ahead Adder
- Carry Save Adder
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2. Why is the ripple carry adder relatively slow compared to other types of adders?
- Because multiple carry-save stages are required to complete the addition.
- Because the carry must propagate through all stages, causing a delay of two gate delays per stage in the worst case.
- Because it uses half adders instead of full adders, increasing the latency.
- Because it requires a parallel prefix structure for carry propagation.
Answer :-
3. A 24-bit ripple carry adder is realized using 24 identical full adders if the carry propagation delay of each FA is 7.5 ns and the sum propagation delay of each FA is 22.5 ns. What will the worst-case delay (in ns) of this 24-bit adder?
- 180 ns
- 195 ns
- 202.5 ns
- 210 ns
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4. Which of the following represents logic values of Carry generation (C_G) and carry propagation (C_P) after the addition of A1 and B1 bits in an adder circuit if A3A2A1A0 = 0011 and B3B2B1B0 = 1000 are inputs to the adder?
- C_G =Logic 0 ; C_P = Logic 0
- C_G =Logic 0 ; C_P = Logic 1
- C_G =Logic 1 ; C_P = Logic 0
- C_G =Logic 1 ; C_P = Logic 1
Answer :-
Q.No.5 – 6 follows the following assumptions:
A 32 bit carry select adder is designed using 4 bit carry look ahead modules and 4 bit 2:1 multiplexers. Delay of an optimized 4 bit carry look-ahead adder is 6 units and delay of 4 bit 2:1 mux is 1 unit. Assume no carry in.
5. How many multiplexers would be required in the design of a 32 bit carry select adder?
- 4
- 5
- 6
- 7
- 8
- 9
- 10
- More than 10
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6. What would be the delay of 32 bit carry select adder
- 6 units
- 7 units
- 12 units
- 13 units
- 14 units
- 37 units
- None of these
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7. For adding multiple operands, carry save adder has higher propagation delay than ripple carry adder?
- True
- False
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8. In the declaration wire [15:0] sum; how many bits can the sum wire hold?
- 8 bits
- 4 bits
- 16 bits
- 32 bits
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9. Which of the following statements correctly assigns the most significant bit of a 16-bit wire sum to a wire T?
- T = sum[0];
- T = sum[8];
- T = sum[15];
- T = sum[12];
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10. In a Verilog module, given the following statements:
A = {a4, a3, a2, a1};
sum = {16{1’b1}};
Which of the following statements is true about the given code?
- sum will be assigned a 16-bit value with all bits set to 1.
- A is a 16-bit concatenated value from a4, a3, a2, and a1.
- {16{1’b1}} represents a 16-bit value where each bit is alternating 0s and 1s.
- The value of sum will be displayed as %d in binary format.
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